Scan tests are implemented to test circuit behavior, such as behavior caused by manufacturing defects in digital logic based devices. For example, modern microprocessors are implemented using tens of millions of logic gates. Scan tests are used to test the logic gates for faults.
In a conventional scan test, a test pattern is generated to test a prospective device. The test pattern may include a sequence of zeros and ones defined to test various logic gates. An automated test pattern generator (ATPG) is typically used to generate the test pattern. The ATPG analyzes a circuit model (i.e., called a netlist) of a digital logic based device such as a microprocessor (i.e., chip) and identifies a set of potential fault locations or sites on the chip. The ATPG then generates the test patterns necessary to test the device.
Storage elements (i.e., flip-flops) on the device are connected serially during scan test operations into a scan chain or scan chain segment. The test pattern is often generated in a one-to-one relationship with the scan chain segment. For example, if the scan chain is 10 flip-flops long the test pattern may be generated with 10 bits, one bit associated with each flip-flop.
The test pattern is introduced through an input data pin. The test pattern is shifted into the scan chain segment serially, one bit per clock cycle. After a selected number of capture clock cycles, the resulting state of the test is then shifted out through an output pin. As the test pattern is shifted out of the scan chain segment, another test pattern is shifted into the scan chain segment. Each test pattern is generated with the intention of discovering faults in the logic surrounding the flip-flops in the scan chain segment. Therefore, the ATPG generates patterns that will place specific states on the flip-flops in the scan chain so that targeted faults in the surrounding logic can be identified.
Modern integrated circuit architectures include a tremendous amount of logic and gates that need to be tested. Thus, a tremendous amount of data is generated with each test and a substantial number of test patterns have to be generated to test a device. For example, ATPG programs may run for weeks to create test patterns for large, complex circuits.
Since the flip-flops are connected in a serial chain and each bit in the test pattern or vector is shifted into the scan chain at the rate of one bit per clock cycle, when there are tens of millions of bits, it takes a substantial amount of time to shift the test patterns into the scan chain. The cost of performing the scan chain test is directly proportional to the amount of time required to perform the test. As a result, a number of techniques have been developed to optimize the time and lower the cost associated with scan chain testing.
As the complexity of ASICs increases, the number of flip-flops, and thus the associated scan test length, also increases. Further, ASIC architectures may include additional technologies, such as Serializer/De-serializers (SERDES); buffered memory devices; phase-locked loop based timing circuits among others. Additional technologies, such as the SERDES, tend to reduce the number of input/output (I/O) pins available for inputting and outputting the test pattern. These two factors combine to increase the number of clock cycles needed to perform scan tests. As a result of the fewer, longer scan chains, the cost of the scan test increases.
To reduce the test time and cost, a variety of conventional scan compression techniques have been developed. In these scan compression techniques, a test pattern is decompressed on chip after being input, used to perform a scan test, and then the response is compressed on chip before being output. As a result, although limited I/O pins are available, a large variety of test patterns can be generated to test the targeted faults in a limited amount of time. Unfortunately, even the generation of compressed scan test patterns is expensive and time consuming. For example, each time an ASIC design changes (e.g., logic circuits are synthesized or implemented differently than in a previous version), the scan test patterns or test vectors must be regenerated to exercise and confirm desired operation of the ASIC. This is true even when separate ASICs include identical support functions. The problem is further complicated when support functions and application specific logic are to be tested separately. For example, it is sometimes the case that additional technologies or support functions must be tested independently from an ASIC's core logic. Thus, scan chains or test vectors must be generated for each separate test.
Thus, improvements in ASIC testing are required, specifically in the development of systems and methods that enable improved efficiencies in test generation and re-use across disparate synthesized versions of an ASIC and across dissimilar ASICs that share one or more support functions or blocks.